Basic VLSI Design — DU B. Sc. (Hons) Electronics Previous Year Question Papers

Explain how the physical defects can be realised as electrical and logical faults in the circuits. (6) : Basic VISI Design : V (Under NEP UGCF 1. a) Draw the output characteristics of MOSFET. Define Triode, Deep Triode and Saturation regions. (3) b. For a P.SPICE model having following instruction: Explain the significance of each term. c. Calculate the noise margins of a CMOS inverter given VoL=0.1V, VoH=4.9V, V[L=1.OV and V]H=2.0 d. Define rise time, fall time and time period of a dynamic wave form. (3) 7. a. Explain the construction of the one-transistor DRAM cell. Also explain the various operations of the DRAM Cell (6) b. Design a n-MOSFET programmable ROM that contains the following data: (6) Address Data b. Using any two input logic gate design, explain the merits and demerits of pass transistor logic over c. Sketch the CMOS circuit diagram to implement function, F=(,4.B)+(C.D) . (6) 6. a. Draw two-input XOR gate using CMOS logic and explain its working for different truth table input conditions. Also, explain why it is referred to as ? c. Consider the logic shown in the diagram and draw the CMOS based circuit for the function F (6) e. In static CMOS logic circuit design, why PMOS logic array and NMOS logic array are referred to as Pull-Up Network (PUN) and Pull-Down Network (PDN)? (3) f. What is scan based techniques? 3 2. (3) 2. a. Considering gradual channel approximation derive the expression `for Drain current equation of the MOSFET having the effective channel length `L'. (6) b. What is `Pinch-off' condition in MOSFET. Explain how it can be achieved. What will happen if drain to source voltage is increased after the channel is . pinched off. (6) c. For a particular IC fabrication process, the transconductance parameter K'n = 50#z4 / 7'2 , and VT[.[=1V. In an application in Which VGs=VDs=5V, a drain current of 0.8mA is required of a device of minimum length of 2.LLm. What value of channel width must the design use? \ (6) 3. a. What is process technology parameter? How it is related to Channel Length Modulation? Determine the expression for output conductance and show it strongly depends on channel length. (6) b. What are interface Traps. De.rive the expression for Threshold v-oltage, showing the sign of various components of Threshold voltage for N-channel and p channel devices. (6) = 100 HA/V2, Kp = 40 HA/V2. Find the switching 4. a. Explain the principle of operation of a CMOS inverter. Discuss- the roles of the load and driver transistors and how the inverter performs logic b. Derive the expression for critical voltages for a i-MOs inverter circuit with resistive load (6) c. Estimate the power consumption of a CMOS inverter with load capacitance 5pF, operating at 100 5. a. Derive the expression for Noise Margins (NMH and NML) of a CMOS inverter in terms of the transfer characteristics (6)