CMOS Digital VLSI Design (ELEDSE7E) — DU B. Sc. (Hons) Electronics Previous Year Question Papers

Instruction for Candidates Q1 a) What are the key differences in VHDL and Verilog? b) What are the main parts of a VHDL code. Write a short code for a two input AND gate with delay of 5 units in Verilog. d) What are four basic values of Verilog value set? Why is refresh circuitry needed in a DRAM cell? f) What is LVS and parameter extraction in VLSI? 3x6 Q2 a) Compare the three types of modelling in VHDL. Discuss briefly with examples. 6 b) Write a code in VHDL to implement Full Adder. 7 c) Describe the various data objects in VHDL. Q3 a) Compare the statements 'WHEN ELSE' and "WITH WHEN SELECT' with the help of an example. 6 b) Discuss with the help of an example, the role of components and port mapping in c) Briefly explain the various relational and logical operators in VHDL. 5 Q4 a) What will be the execution sequence and output of statements in the code of a stimulus block given below: module stimulus; reg x,y,a,b,m; initial initial 1=1 b0; begin #25 b=1'b0; end initial begin #25 y=1'b1; end initial #50 $finish; endmodule 6 Write a Verilog code for 4X1 MUX using gate level modelling. 7 c) Describe Port connection rules in Verilog. 5 Q5 a) How conditional operators can be used in Verilog for behavioural modelling. Explain with example. b) Briefly describe hierarchy and the four levels of abstraction in Verilog. 6 c) When we have many alternatives to choose which one is better using nested se-if or case statement in Verilog? Explain with exampl 5 What are the advantages and disadvantages of a 6T full CMOS SRAM? 6 What is access time penalty in 6T Full CMOS SRAM cell and how is it reduced? 5 Draw and explain the typical voltage waveforms associated with 3-T DRAM cel luring four consecutive operations: write "1," read "1," write "O," and read "O. 7 Cell Metal 2 edthrough GND VDD Metal 1/ Based on the given layout diagram, What is the CMOS VLSI design methodology used? What does A,B,C and D signify? Explain the function of each labelled b) What are the various steps involved in the ASIC Design Flow? Elaborate on Front-end and Back-end design. 6 Active area Identify the regions from R1 to R9 and provide their typical value based on the 2 based scaling design rules 6