CMOS Digital Integrated Circuit Design (INDSE7B) — DU B.Sc. (Hons) Instrumentation Previous Year Question Papers

CMOS Digital Integrated Circuit Design B.Sc. (H) Instrumentation (DSE) Q.1 (a) Explain operation of complementary MOs inverter in the transition region (3) (b) Explain the working principle of a cMOs transmission gate. Why is it preferred over a single NMOS or PMOS switch? (c) Define a .sequential circuit. How does it differ from a combinational circuit in CMOS logic design? (d) What is the differencebetweenvolatile andnon-volatile memory? Give one (3) example of each. (e) In a CMOS inverter, if the voltage transfer characteristic has V|H = 3V and V|L = 1V, calculate the noise margins NMH and NML given VDD = 5V (assume VOH a VDD and VOL ~~ ov). (I) Ifa processor has a 64K x 8-bit memory, how many address lines are required? (3) Q.2 (a) Draw and explain the Voltage Transfer Characteristics (VTC)of a CMOS (8) a) Discuss calculationof gain of a CMOS inverter from its voltage transfer (6) characteristics. Derive an expression for #:i and explain its significance near the threshold point. (c) Describe the static behaviorof a CMOS inverter when the input voltage (4) transitions from low to high. Q.3 (a) Implement the following Boolean function using complementary MOs logic. (6) (b) Describe the design and operation of CMOS NOR gate. Discuss its pull-up (6) network configurations. (c) Implement a 2 X 1 Multiplexer using Transmission gates and interpret its (6) operation using different input combinations Q.4 (a) Realize Edge triggered D-Flip-Flop using Transmission gates and explain its (6) (b) Draw diagram and explain the implementation of SR latchusing (6) Complementary MOS NOR gates. (c) Explain the working of a cMOs clocked flip-flop circuit. Compare its operation for positive and negative edge triggering. (6) Q.5 (a) Discuss memory classificationusing a diagram. Explain hierarchical (6) organizati on from registers to secondary storage. (b) Describe the internal structure and working of aROM cell array. Explain how (6) data is read and the significance of address decoding. (c) List different types of RAM cells. Draw and explain the operation of a single bit (6) dynamic ~ cell. Q.6 (a) Write the logic equation for a 1-bit CMOS full adderarid derive the output (6) expressions for Sum and Carry. (b) Differentiate between SRAM and DRAMbased on cell structure and data (6) retenti on method. (6) Q.7 (a) Design a XOR gate using Transmission gate Logic. (b) Derive the expression for the switching threshold (VM) of a cMOs inverter. (c) Differentiate between Dynamic cMOs and static CMOS. (6)